In 2003, Professor Dr.-Ing. Jürgen Teich took up the newly established chair in Hardware-Software-Co-Design within the Faculty of Computer Science. Professor Teich received his masters degree (Dipl. Ing.) in 1989 from the University of Kaiserslautern (with honours). From 1989 to 1993, he was a PhD student at the University of Saarland, Germany from where he received his PhD degree (summa cum laude). In 1994, he joined the DSP design group in the Department of Electrical Engineering and Computer Sciences (EECS) at UC Berkeley where he was working in the Ptolemy project (PostDoc). From 1995-1998, Jürgen Teich held a research position at Institute of Computer Engineering and Communication Networks Laboratory (TIK) at ETH Zürich, Switzerland, finishing his Habilitation entitled Synthesis and Optimization of Digital Hardware/Software Systems in 1996. From 1998-2002, he was full professor in Electrical Engineering and Information Technology department of the University of Paderborn, Germany, holding a chair in Computer Engineering. In Paderborn he also worked in two Collaborative Research Centers sponsored by the German Science Foundation (DFG). Since 2003, he is appointed full professor in the Computer Science Institute of the University Erlangen-Nuremberg arranging the organizational structure of the new chair in Hardware-Software-Co-Design in Erlangen. Mr. Teich has been a member of multiple program committees of well-known conferences such as the DATE (Design, Automation, and Test in Europe) as well as editor of several books. Furthermore, he has started a successfull German research initiative on reconfigurable systems in May 2003. Since 2004, Prof. Teich is also elected reviewer of the German Science Foundation (DFG) for the area of Computer Architectures and Embedded Systems. Since November 2004, Prof. Dr. rer. nat. Rolf Wanka occupies the professor position for efficient algorithms and combinatorial optimization at in the Institute of Computer Science.

The research area of the chair Hardware-Software-Co-Design covers all aspects of the systematic construction (CAD) of embedded systems. Area of expertise of the chair is scheduling, placement, routing and load balancing in embedded systems. The research interests include in particular: innovative and adaptive computer architectures and application specific instructionset processors (ASIPs, RISPs) their programming as well as the development of methods and tools such as simulators, compilers and prototypes for these devices. Likewise discrete optimization methods, in particular local and global search methods, linear programming, multiobjective optimization problems and their application for optimization of hardware software systems.

Groups

• System-Level Design Automation Group

Here, the most challenging problems in automatically designing embedded hardware-software-systems at the system level are considered. In particular, this includes modelling, system synthesis, optimization, and verification of embedded systems. The goal of the System-Level Design Automation Group is the support of new design paradigms like adaptive applications and hardware reconfigurable architectures. For these new technologies there is still a lack of a seamless design flow. Even more, recent events demand novel formal methods at higher levels of abstraction. Only with these methods, new products can be designed “first-time-right” and in an even shorter time to market. Therefore it is also mandatory to integrate new design methodologies into a language-based design flow. Currently, the System-Level Design Automation Group works on two projects covering the most important tasks in design automation of embedded hardware-software-systems.

• Architecture and Compiler Design

Life cycles of technical products are continuously decreasing, especially in the area of computer technology. This cascading effect becomes possible by the fact that computers themselves are used to design new powerful microprocessors for the next computer generation. Thus, the design time for new generations of microprocessors decreases rapidly.
Beyond that, in the last years, microprocessors are employed more and more in products where the presence of microprocessors is not obvious: Cellular phones, PDAs, medical technology, entertainment electronics, and in the automotive world.
Unlike typical computers like PCs and workstations, these embedded systems are specialized to a certain class of applications and highly optimized with respect to computation speed, cost, interface bandwidth, energy consumption, etc. Beside production costs, development cost and shorter time-to-market cycles have become important.
The goal in our working group “Architecture and Compiler Design” is to shorten the design cycle when developing application specific processors. Here, the following research areas are considered: CAD tools for modelling, simulation, and the automatic generation of architectures, and compilers and mapping methodologies for these architectures.
Both micro programmable processors and dedicated hardware are investigated. The goal when designing micro programmable application specific processors is an architecture/compiler co-generation optimized for a whole class of algorithms (benchmark). Many computational applications may also implemented directly in one dedicated massively parallel system, i.e., one highly optimized system (e.g., a co-processor) realizes exactly one application.
From these different target architectures (programmable or dedicated) a trade-off between hardware and software solutions is resulting. Here, one solution might be the consideration of reconfigurable architectures. Therefore, reconfigurable arrays and processors are part of our actual research.

• Reconfigurable Computing Group

The goal of our research activities is the investigation of fundamentals for the design of computing systems that are able to adapt their behaviour and structure to changing operating and environmental conditions, time-varying optimization objectives, and physical constraints like changing protocols, new standards, or dynamically changing operation conditions of technical systems. Due to constantly decreasing lifetime of technical products, systems able to be reconfigured at different levels of hardware granularity are becoming more and more important. Only those systems are able to provide optimal solutions for applications with constraints and requirements not clearly defined at design time and for which high redesign time should be avoided. It is possible with reconfigurable solutions to optimize the production cost of digital products, particularly those produced in low volume. The expected research results will be used as foundation for the development of self-reconfigurable or self-repairing systems in the feature. Our central research topics are the study of mechanisms and efficiency of reconfiguration, the investigation of models and languages to support hardware reconfigurability as well as the development of viable reconfigurable architectures, and the identification and implementation of suitable reconfigurable applications. Our research is supported mostly by the German Research Foundation (DFG) with the funding of two different projects: The project ReCoNodes and the project ReCoNets. Those two projects are part of the German research per excellence program on reconfigurable systems (SPP 1148) which was set-up in June 2003.

• Associated project group Hardware Software Codesign (with Fraunhofer Institute of Integrated Circuits (IIS))
  

The Hardware Software Codesign group is part of the Electronic Imaging group which offers a wide range of applications for intelligent embedded systems. In the future, it will be a great challenge to handle complex technical systems consisting of hardware and software components as well. For many known problems arising during the system design phase, there are powerful tools, e.g. for synthesis and simulation of the particular components of such a complex system. However, so far, there are no tools for automatic interface synthesis, for overall-verification of the complete system, and for finding design alternatives in early design phases. In case inherent intelligence is a design target, the system must be dynamically self-reconfigurable during runtime. Typical application examples can be found in intelligent image processing systems, content based data processing, and self-learning and self-repairing devices.
The application domain of such systems is in the area of communicating embedded systems in body area networks, automotive electronics, and intelligent camera systems. In the following, the recently started work will be described. Since May 2003 we have explored novel implementations of the Motion JPEG-2000 standard, here especially parallel implementations of entropy encoders. We aim for a high-performance design consisting of microprocessors and FPGAs, allowing for a coding rate of more than 25 frames per second for a resolution of 1920x1080 pixels. In autumn 2003 started cooperative work in the area of intelligent cameras (CogniCam). We study concepts of cameras capable of intelligent and adaptive functions. These intelligent functions comprise active control of dynamic range, display window, color adjustment, resolution, exposure speed, focus, brightness, and zoom. An important requirement is a highly efficient implementation of these functions. In cooperation with the department IC-Design Digital (ICDD) we work in the area of system level design with SystemC. The goal is to examine representations of design refinements in SystemC, modelling and simulation of complex designs.

• DaimlerChrysler AG, Esslingen

• ETH Zürich, Institut für Technische Informatik und Kommunikationsnetze (Prof. Dr. L. Thiele)

• ETH Zürich, Institut für Technische Informatik und Kommunikationsnetze (Dr. M. Platzner und Dr. E. Zitzler)

• Fraunhofer Institut für integrierte Schaltungen (IIS), Erlangen

• Fraunhofer Institut für Zuverlässigkeit und Mikrointegration (IZM), Paderborn

• IBM Deutschland Entwicklung GmbH, Böblingen

• Infineon AG, München

• Lucent Technologies GmbH, Nürnberg

• PACT Technologies AG, München

• Technische Universität Braunschweig, Institut für Datenverarbeitungsanlagen (Prof. Dr. R. Ernst)

• Technische Universität Braunschweig, Mathematik (Prof. Dr. S. Fekete)

• Universität Karlsruhe, Forschungszentrum für Informatik (FZI) (Prof. Dr. J. Becker)

• University of Maryland, UMIACS (Prof. Dr. S. S. Bhattacharyya)

• AConFPGA – Approximate Computing on FPGAs
  
• Algorithms for Combinatorial Problems
  
• AutonmotiveSensors@ESI
  
• CogniPower - Cognitive Power Control for Mobile Devices
  
• Efficient Use of Resources in Parallel Systems
  
• Design of dedicated massively parallel systems
  
• Entwurf und Evaluierung hochverfügbarer Ethernet-basierter E/E-Architekturen für latenz- und sicherheitskritische Anwendungen
  
• Parallelization and Resource Estimation of Algorithms for Heterogeneous ADAS Architectures
  
• Partikelschwarm-Optimierung
  
• CRC/Transregio 89, Project A1: Basics of Invasic Computing
  
• CRC/Transregio 89, Project A4: Design-Time Characterisation and Analysis of Invasive Algorithmic Patterns
  
• CRC/Transregio 89, Project B2: Invasive Tightly-Coupled Processor Arrays
  
• CRC/Transregio 89, Project B5: Invasive NoCs – Autonomous, Self-Optimising Communication Infrastructures for MPSoCs
  
• CRC/Transregio 89, Project C2: Simulative Design Space Exploration
  
• CRC/Transregio 89, Project C3: Compilation and Code Generation for Invasive Programs
  
• CRC/Transregio 89, Project Z2: Validation and Demonstrator
  
• CRC/Transregio 89, Project Z: Central Services of the Transregional Collaborative Research Centre and Public Relations
  
• SPP 1648 - Software for Exascale Computing, Project "ExaStencils - Advanced Stencil-Code Engineering"
  
• SystemCoDesigner: System level design space exploration for embedded systems
  
• SysteMoC: Representing models of computation in SystemC
  

• 2D/3D Video Surveillance
  
• AIS - Autonome Integrierte Systeme
  
• Architekturmodellierung und Exploration von Algorithmen für die medizinische Bildverarbeitung
  
• Automatic Test Case Generation from Fromale Specifications
  
• Image Pipeline on GPUs
  
• Design and Simulation of Complex Intercomponent Communication in SoCs
  
• DFG-Graduiertenkolleg 633 – Interdisziplinärer Entwurf verlässliche Multitechnologiesysteme
  
• DFG-Graduiertenkolleg PaSCo – Paderborner Institute of Scientific Computation
  
• DFG-Graduiertenkollegs HNI – Automatische Rekonfiguration in verteilten Systemen
  
• DFG Project AEOS: Actor-Oriented Synthesis and Optimization of Digital Hardware/Software-Systems at the Electronic System Level
  
• DFG Project CoMap: Co-Design of Massively Parallel Embedded Processor Architectures
  
• DFG-Projekt: Organic Bus
  
• DFG-Schwerpunktprogramm 1040 Eingebettete Systeme, „Modelle und Methoden zur Synthese und Optimierung gemischt reaktiv/transformativer Systeme“
  
• Extended diagnostic capabilities to improve the analyzability of electrical deficiencies in automotive systems
  
• Entwicklung einer FPGA-Erweiterungsplatine für die medizinische Bildverarbeitung
  
• Design of special purpose processor architectures
  
• Entwurf und Optimierung eines CAM-/Crank-Prozessors
  
• Entwurfsmethodik für gemischt zeitgesteuerte und ereignisgetriebene Steuergerätearchitekturen - Modellierung, Optimierung und Implementierung
  
• Entwurfsraumexploration und Implementierung von Signalverarbeitungsalgorithmen
  
• ESI-Project: Ganzheitlicher Entwurf von Fahrerassistenzsystemen im Automobilbereich
  
• ESI-Projekt: High-Level-Modellierung von Bus-Controllern und -Systemen in der Automatisierungstechnik
  
• ESI-Project: Reliable FPGA-based Adaptive Systems for Space and Avionics Applications
  
• Multi- and Many-Core Evaluation
  
• EVOLIVO - EVOlutionary Learning by Intelligent Variation and choice of suitable Operator sets
  
• Evolutionäre vernetzte E/E-Architekturen
  
• Dynamically Reconfigurable SQL Accelerator based on FPGAs
  
• Generating C/C++ Models from a formal System Specification
  
• GRK 1773 - Teilprojekt B3: Heterogene Bildsysteme
  
• Hardware-Software-Co-Design kamerabasierter Fahrerassistenzsysteme
  
• Integral Safety Architecture – Modelling, Analysis, Optimization, and Variant Management
  
• KoDaK - Coexistence of different Traffic Classes in Vehicles and Airplanes
  
• Konzepte zur Realisierung, Optimierung der Auslegung und Prototypisierung einer modularen und konfigurierbaren elektronischen Datenkonsolidierungseinheit für den Einsatz in zivilen Flugzeugen
  
• Performance Assessment of InfiniBand HCA models
  
• MEAT - Multi-objective Exploration of Architecture Tradeoffs
  
• MMSys: Motion Management System
  
• Modellierung und Simulation des InfiniBand-Protokolls
  
• Multikriterielle Optimierung von digitalen Hardware/Software-Systemen
  
• PowerEval – Leistungsevaluierung und -optimierung zukünftiger mobiler Funkplattformen
  
• Programmierverfahren zur Generierung parallelen echtzeitfähigen Codes in der diagnostischen Bildverarbeitung
  
• Raum- und Zeitoptimierung der Vorlesungen der Technischen Fakultät
  
• ReCoNets – Design methodology for embedded system made upon small networks of hardware reconfigurable nodes and connections
  
• ReCoNodes – Optimization methodologies for reconfiguration management on reconfigurable hardware nodes
  
• ReCoNodes – Optimization methodologies for reconfiguration management on reconfigurable hardware nodes
  
• ReKoSys: Kognitive eingebettete Systeme auf Basis dynamisch rekonfigurierbarer Hardware
  
• High-speed Serial Interconnects for Medical Image Processing
  
• SFB 694 - Integration elektronischer Komponenten in mobile Systeme, Teilprojekt B5: Fertigungsorientierte Entwurfsmethodik für Software eingebettet in Komponenten mobiler Systeme
  
• CRC/Transregio 89, Project C2: Simulation of Invasive Applications and Invasive Architectures
  
• SFB376 – Massive Parallelität: Algorithmen, Entwurfsmethoden, Anwendungen, "Teilprojekt B5, Algorithmisch Spezialisierte Systeme"
  
• SFB614 – Selbstoptimierende Systeme des Maschinenbaus, „Teilprojekt A1, Modellbasierte Selbstoptimierung“
  
• SFB614 – Selbstoptimierende Systeme des Maschinenbaus, „Teilprojekt C1, Hardware-Rekonfiguration“
  
• Sicherheit in Eingebetteten IP-basierten Systemen (SEIS)
  
• SpecVer: Specification for Verification of complex systems
  
• SPP 1500 - Dependable Embedded Systems, Associated Subproject "CRAU - Compositional System Level Reliability Analysis in the Presence of Uncertainties"
  
• SystemC-basierte Performance-Abschätzung der System z-Architektur
  
• Untersuchung der Sicherheit der Kommunikation und Datenverarbeitung im Automobil
  
• Untersuchungen und Arbeiten im Bereich SystemC Schulungen und IC-Design